MC68HC705JP7 Datasheet, PDF (99/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
Port B
3. If the SIOP function is terminated by clearing the SPE bit in the
SCR, then the last conditions stored in the DDRB6, PDIB6, and
PB6 register bits will then control the PB6/SDI pin.
4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in
the SCR and the DDRB6 bit must be cleared. Depending on the
external application, the pulldown device may also be disabled by
setting the PDIB6 pulldown inhibit bit.
5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the
SCR must be cleared and the DDRB6 bit must be set. The
pulldown device will be disabled in this case.
7.4.9 PB7/SCK Logic
The PB7/SCK pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-12. The operations of
the PB7/SCK pin are summarized in Table 7-3.
SERIAL DATA CLOCK (SCK)
READ $0005
CLOCK SOURCE (MSTR)
SERIAL ENABLE (SPE)
WRITE $0005
DATA DIRECTION
REGISTER B
R
BIT DDRB7
WRITE $0001
READ $0001
WRITE $0011
RESET
PORT B DATA
REGISTER
BIT PB7
PULLDOWN
REGISTER B
R
BIT PDIB7
MASK OPTION REG. ($1FF1)
Figure 7-12. PB7/SCK Pin I/O Circuit
PB7
SCK
PULLDOWN
DEVICE
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Parallel Input/Output
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