MC68HC705JP7 Datasheet, PDF (166/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Timer
PB3
AN3
TCAP
READ
ICRH
INPUT
SELECT
MUX
CPF2
FLAG
BIT
FROM
ANALOG
SUBSYSTEM
ICEN
CONTROL
BIT
RESET
EDGE
SELECT
& DETECT
LOGIC
LATCH
ICRH ($0014) ICRL ($0015)
16-BIT COUNTER
INPUT CAPTURE (ICF)
INTERNAL
DATA
BUS
READ
ICRL
÷4
INTERNAL
CLOCK
(OSC ÷ 2)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 11-6. Timer Input Capture Block Diagram
Advance Information
166
The input capture registers are made up of two 8-bit read-only registers
(ICRH and ICRL) as shown in Figure 11-7. The input capture edge
detector contains a Schmitt trigger to improve noise immunity. The edge
that triggers the counter transfer is defined by the input edge bit (IEDG)
in the TCR. Reset does not affect the contents of the input capture
registers.
Address: $0014
Bit 7
6
Read: Bit 15
14
Write:
Reset:
5
4
3
2
13
12
11
10
Unaffected by reset
1
Bit 0
9
Bit 8
Address: $0015
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 11-7. Input Capture Registers (ICRH and ICRL)
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Programmable Timer
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