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MC68HC705JP7 Datasheet, PDF (120/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit
Freescale Semiconductor, Inc.
Analog Subsystem
CPFR2
Writing a logic 1 to this write-only flag clears the CPF2 flag in the ASR.
Writing a logic 0 to this bit has no effect. Reading the CPFR2 bit will
return a logic 0. By default, this bit looks cleared following a reset of
the device.
1 = Clears the CPF2 flag bit
0 = No effect
NOTE:
CPFR1
Writing a logic 1 to this write-only flag clears the CPF1 flag in the ASR.
Writing a logic 0 to this bit has no effect. Reading the CPFR1 bit will
return a logic 0. By default, this bit looks cleared after a reset of the
device.
1 = Clears the CPF1 flag bit
0 = No effect
The CPFR1 and CPFR2 bits should be written with logic 1s following a
power-up of either comparator. This will clear out any latched CPF1 or
CPF2 flag bits which might have been set during the slower power-up
sequence of the analog circuitry.
If both inputs to a comparator are above the maximum common-mode
input voltage (VDD –1.5 V), the output of the comparator is indeterminate
and may set the comparator flag. Applying a reset to the device may only
temporarily clear this flag as long as both inputs of a comparator remain
above the maximum common-mode input voltages.
VOFF
This read-write bit controls the addition of an offset voltage to the
bottom of the sample capacitor. It is not active unless the OPT bit in
the COPR at location $1FF0 is set. Any reads of the VOFF bit location
return a logic 0 if the OPT bit is clear. During the time that the sample
capacitor is connected to an input (either HOLD or DHOLD set), the
bottom of the sample capacitor is connected to VSS. The VOFF bit is
cleared by a reset of the device. For more information, see 8.11
Sample and Hold.
1 = Enables approximately 100 mV offset to be added to the
sample voltage when both the HOLD and DHOLD control bits
are cleared
0 = Connects the bottom of the sample capacitor to VSS
Advance Information
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Analog Subsystem
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