MC68HC705JP7 Datasheet, PDF (39/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Memory
Input/Output Registers
Addr.
Register
Bit 7
6
5
$000A
SIOP Control Register ^Read: _SPIE
(SCR) Write:
See page 145. _{Reset: 0}
SPE LSBF
0
0
$000B
SIOP Status Register ^{Read: SPIF DCOL}
0
(SSR) Write:
See page 148. _{Reset: 0}
0
0
$000C
SIOP Data Register ^Read: _{Bit 7}
6
5
(SDR) Write:
See page 149. _Reset:
$000D ^{IRQ Status and Control Register Read:} IRQE
OM2
OM1
(ISCR) Write:
See page 58. _{Reset: 1}
1
0
$000E
PEPROM Bit Select Register ^Read:
(PEBSR) Write:
See page 177. _Reset:
PEB7
0
PEB6
0
PEB5
0
$000F
PEPROM Status and Control ^{Read: PEDATA}
0
PEPGM
Register (PESCR) Write:
See page 178. _{Reset: U}
0
0
$0010
Pulldown Register Port A and ^Read:
Port C⁽¹⁾ (PDRA) Write:
See page 87. _Reset:
PDICH
0
PDICL
0
PDIA5
0
$0011
Pulldown Register B ^Read:
(PDRB) Write:
See page 92. _Reset:
PDIB7
0
PDIB6
0
PDIB5
0
$0012
Timer Control Register ^Read: _ICIE
OCIE
TOIE
(TCR) Write:
See page 170. _{Reset: 0}
0
0
= Unimplemented
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
4
3
2
1
Bit 0
0
MSTR
CPHA SPR1 SPR0
SPIR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
Bit 0
0
IRQF
0
0
0
R
IRQR
0
0
0
U
0
PEB4 PEB3 PEB2 PEB1 PEB0
0
0
0
0
0
0
0
0
0 PEPRZF
R
R
R
0
0
0
0
1
PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
0
0
0
0
0
PDIB4
0
0
PDIB3
0
0
PDIB2
0
0
PDIB1
0
IEDG
PDIB0
0
OLVL
0
0
0
U
0
R = Reserved U = Unaffected
Figure 2-3. Register Summary (Sheet 2 of 4)
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Memory
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Advance Information
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