English
Language : 

MC68HC705JP7 Datasheet, PDF (32/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit
Freescale Semiconductor, Inc.
General Description
1.8 RESET Pin
The RESET pin can be used as an input to reset the MCU to a known
startup state by pulling it to the low state. It also functions as an output
to indicate that an internal COP watchdog, illegal address, or low-voltage
reset has occurred. The RESET pin contains a pullup device to allow the
pin to be left disconnected without an external pullup resistor. The
RESET pin also contains a steering diode that, when the power is
removed, will discharge to VDD any charge left on an external capacitor
connected between the RESET pin and VSS. The RESET pin also
contains an internal Schmitt trigger to improve its noise immunity as an
input.
1.9 IRQ/VPP Pin
The IRQ/VPP input pin drives the asynchronous IRQ interrupt function of
the CPU. The IRQ interrupt function uses the LEVEL bit in the MOR to
provide either negative edge-sensitive triggering or both negative
edge-sensitive and low level-sensitive triggering. If the LEVEL bit is set
to enable level-sensitive triggering, the IRQ/VPP pin requires an external
resistor to VDD for “wired-OR” operation. If the IRQ/VPP pin is not used,
it must be tied to the VDD supply. The IRQ/VPP pin contains an internal
Schmitt trigger as part of its input to improve noise immunity.
The voltage on this pin may affect operation if the voltage on the
IRQ/VPP pin is above VDD when the device is released from a reset
condition. The IRQ/VPP pin should only be taken above VDD to program
an EPROM memory location or personality EPROM bit. For more
information, refer to 15.14 PEPROM and EPROM Programming
Characteristics.
NOTE:
Each of the PA0–PA3 I/O pins may be connected as an OR function with
the IRQ interrupt function by the PIRQ bit in the MOR. This capability
allows keyboard scan applications where the transitions or levels on the
I/O pins will behave the same as the IRQ/VPP pin, except that active
transitions and levels are inverted. The edge or level sensitivity selected
by the LEVEL bit in the MOR for the IRQ/VPP pin also applies to the I/O
Advance Information
32
MC68HC705JJ7 • MC68HC705JP7 — REV 4
General Description
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA