MC68HC705JP7 Datasheet, PDF (162/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Timer
11.3 Timer Registers
The functional block diagram of the 16-bit free-running timer counter and
timer registers is shown in Figure 11-2. The timer registers include a
transparent buffer latch on the LSB of the 16-bit timer counter.
Advance Information
162
READ
TMRH
RESET
LATCH
TMRL ($0019)
READ
TMRH ($0018)
TMR LSB
$FFFC
16-BIT COUNTER
÷4
OVERFLOW (TOF)
READ
TMRL
INTERNAL
CLOCK
(OSC ÷ 2)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
$0012
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 11-2. Programmable Timer Block Diagram
The timer registers (TMRH and TMRL) shown in Figure 11-3 are
read-only locations which contain the current high and low bytes of the
16-bit free-running counter. Writing to the timer registers has no effect.
Reset of the device presets the timer counter to $FFFC.
The TMRL latch is a transparent read of the LSB until a read of the
TMRH takes place. A read of the TMRH latches the LSB into the TMRL
location until the TMRL is again read. The latched value remains fixed
even if multiple reads of the TMRH take place before the next read of the
TMRL. Therefore, when reading the MSB of the timer at TMRH, the LSB
of the timer at TMRL must also be read to complete the read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and
begins counting after the oscillator startup delay. Because the counter is
16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator
cycles).
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Programmable Timer
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