MC68HC705JP7 Datasheet, PDF (88/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
0 = Lower four port C pins pulldown devices turned on if pin has
been programmed by the DDRC to be an input
PDIA5–PDIA0 — Port A Pulldown Inhibit Bits
Writing to these write-only bits controls the port A pulldown devices.
Reading these pulldown register A bits returns undefined data. Reset
clears bits PDIA5–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on if pin has
been programmed by the DDRA to be an input
7.3.4 Port A External Interrupts
The PIRQ bit in the MOR enables the PA3–PA0 pins to serve as external
interrupt pins in addition to the IRQ/V_PP pin. The active interrupt state for
the PA3–PA0 pins is a logic 1 or a rising edge. A state of the PIRQ bit in
the MOR determines whether external interrupt inputs are
edge-sensitive only or both edge- and level-sensitive. Port A interrupts
are also interactive with each other and the IRQ/V_PP pin as described in
4.6 External Interrupts.
NOTE:
When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ/V_PP pin, not the state of the internal IRQ signal.
Therefore, BIH and BIL cannot test the port A external interrupt pins.
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Parallel Input/Output
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