MC68HC705JP7 Datasheet, PDF (153/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Core Timer
Core Timer Status and Control Register
10.3 Core Timer Status and Control Register
The read/write core timer status and control register (CTSCR) contains
the interrupt flag bits, interrupt enable bits, interrupt flag bit resets, and
the rate selects for the real-time interrupt as shown in Figure 10-2.
Address: $0008
Bit 7
6
5
4
3
2
1
Bit 0
Read: CTOF RTIF
0
0
CTOFE RTIE
RT1
RT0
Write:
CTOFR RTIFR
Reset: 0
0
0
0
0
0
1
1
= Unimplemented
Figure 10-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the core
timer counter roll over from $FF to $00. The CTOF flag bit generates
a timer overflow interrupt request if CTOFE is also set. The CTOF flag
bit is cleared by writing a logic 1 to the CTOFR bit. Writing to CTOF
has no effect. Reset clears CTOF.
1 = Overflow in core timer has occurred.
0 = No overflow of core timer since CTOF last cleared
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. The RTIF enable bit is cleared by writing a
logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears
RTIF.
1 = Overflow in real-time counter has occurred.
0 = No overflow of real-time counter since RTIF last cleared
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Core Timer
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