MC68HC705JP7 Datasheet, PDF (56/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
Freescale Semiconductor, Inc.
IRQ /V_PP
PA3
PA2
PA1
PA0
V_DD
IRQ
LATCH
R
RST
IRQ VECTOR FETCH
V_PP TO
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
IRQ STATUS/CONTROL REGISTER ($000D)
Figure 4-3. External Interrupt Logic
With the edge- and level-sensitive trigger MOR option, a falling edge or
a low level on the IRQ/V_PP pin latches an external interrupt request. The
edge- and level-sensitive trigger MOR option allows connection to the
IRQ/V_PP pin of multiple wired-OR interrupt sources. As long as any
source is holding the IRQ low, an external interrupt request is present,
and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the
IRQ/V_PP pin latches an external interrupt request. A subsequent
interrupt request can be latched only after the voltage level on the
IRQ/V_PP pin returns to a logic 1 and then falls again to logic 0.
Advance Information
56
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Interrupts
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA