MC68HC705JP7 Datasheet, PDF (171/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Timer
Timer Status Register
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
IEDG — Input Capture Edge Select
The state of this read/write bit determines whether a positive or
negative transition triggers a transfer of the contents of the timer
register to the input capture register. This transfer can occur due to
transitions on the TCAP pin or the CPF2 flag bit of voltage comparator
2. Resets have no effect on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
NOTE:
The IEDG bit must be set when either mode 2 or 3 of the analog
subsystem is being used for A/D conversions. Otherwise, the input
capture will not occur on the rising edge of the comparator 2 flag.
OLVL — Output Compare Output Level Select
The state of this read/write bit determines whether a logic 1 or a logic
0 is transferred to the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
1 = Signal to TCMP pin goes high on output compare.
0 = Signal to TCMP pin goes low on output compare.
11.8 Timer Status Register
The timer status register (TSR) shown in Figure 11-11 contains flags for
these events:
• An active signal on the TCAP pin or the CPF2 flag bit of voltage
comparator 2 in the analog subsystem, transferring the contents
of the timer registers to the input capture registers
• A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the PB4/AN4/TCMP pin if
that pin is set as an output
• An overflow of the timer registers from $FFFF to $0000
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Programmable Timer
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