MC68HC705JP7 Datasheet, PDF (53/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Interrupt Processing
4.4 Interrupt Processing
To begin servicing an interrupt, the CPU does these actions:
• Stores the CPU registers on the stack in the order shown in
Figure 4-1
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations as shown in Table 4-1
The return-from-interrupt (RTI) instruction causes the CPU to recover its
register contents from the stack as shown in Figure 4-1. The sequence
of events caused by an interrupt is shown in the flowchart in Figure 4-2.
$0020
$0021
Bottom of RAM
$00BE
$00BF
$00C0
$00C1
$00C2
n
n+1
n+2
n+3
n+4
$00FD
$00FE
$00FF
Bottom of Stack
Condition Code Register
Accumulator
Index Register
Program Counter (High Byte)
Program Counter (Low Byte)
5
4
3
2
1
⇑
Stacking
Order
Unstacking
Order
⇓
1
2
3
4
5
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Interrupts
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