MC68HC705JP7 Datasheet, PDF (116/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog Subsystem
ATD1–ATD2
The ATD1–ATD2 enable bits select one of the four operating modes
used for making A/D conversions via the single-slope method.These
four modes are given in Table 8-3. These bits have no effect if the
ISEN enable bit is cleared. These bits are cleared by a reset of the
device and thereby return the analog subsystem to the manual A/D
conversion method.
Table 8-3. A/D Conversion Options
A/D
Option
Mode
Charge
Control
A/D Options
ISEN ATD2 ATD1 CHG
Current Flow
to/from PB0/AN0
Current
Disabled
source and
discharge
0
X
X
X
Current control disabled,
no source or sink current
disabled
Begin sourcing current
when the CHG bit is set
1
0
0
1 and continue to source
current until the CHG bit
is cleared.
The CHG bit remains set
1
1
0
1 until the next time ICF
occurs.
Automatic
The CHG bit remains
charge and
1
1
1
0 cleared until the next
3
discharge
(OCF–ICF)
time OCF occurs.
The CHG bit remains set
synchronized ₁
1
1
1 until the next time ICF
to timer
occurs.
Advance Information
116
ICEN
This is a read/write bit that enables a voltage comparison to trigger the
input capture register of the programmable timer when the CPF2 flag
bit is set. Therefore, an A/D conversion could be started by receiving
an OCF or TOF from the programmable timer and then terminated
when the voltage on the external ramping capacitor reaches the level
of the unknown voltage. The time of termination will be stored in the
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Analog Subsystem
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