MC68HC705JP7 Datasheet, PDF (94/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
4. If interaction between the port logic and the other module is not
desired, the pin should be configured as an input by clearing the
appropriate DDRB bit. The input pulldown device is disabled by
clearing the appropriate PDRB bit (or by disabling programmable
pulldowns with the SWPDI bit in the MOR).
7.4.6 PB4/AN4/TCMP/CMP1 Logic
The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be
controlled by the OLVL bit from the output compare function of the 16-bit
programmable timer, or be controlled directly by the output of
comparator 1 as shown in Figure 7-9. The PB4 data, the programmable
timer OLVL bit, and the output of comparator 1 are all logically ORed
together to drive the pin. Also, the analog subsystem input channel 4
multiplexer is connected directly to this pin. The operations of PB4 pin
are summarized in Table 7-2.
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
R
BIT DDRB4
WRITE $0001
PORT BDATA
REGISTER
BIT PB4
OLVL
(TIMER OUTPUT COMPARE)
CMP1
(COMPARATOR 1 OUT)
READ $0001
WRITE $0011
RESET
PULLDOWN
REGISTER B
R
BIT PDIB4
ANALOG SUBSYSTEM
INPUT AN4 AND
TIMER OUTPUT COMPARE
PB4
AN4
TCMP
HIGH SINK/
SOURCE CURRENT
CAPABILITY
MASK OPTION REG. ($1FF1)
PULLDOWN
DEVICE
COP REGISTER ($1FF0)
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit
Advance Information
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Parallel Input/Output
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