MC68HC705JP7 Datasheet, PDF (169/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Timer
Output Compare Registers
Writing to the OCRH before writing to the OCRL inhibits timer compares
until the OCRL is written. Reading or writing to the OCRL after reading
the TCR will clear the output compare flag bit (OCF). The output
compare OLVL state will be clocked to its output latch regardless of the
state of the OCF.
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is
written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This
also clears the OCF flag bit in the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown in Table 11-1.
Table 11-1. Output Compare Initialization Example
9B
SEI
DISABLE INTERRUPTS
...
...
.....
...
...
.....
B7
16
STA OCRH INHIBIT OUTPUT COMPARE
B6
13
LDA TSR ARM OCF FLAG FOR CLEARING
BF
17
STX OCRL READY FOR NEXT COMPARE, OCF CLEARED
...
...
.....
...
...
.....
9A
CLI
ENABLE INTERRUPTS
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Programmable Timer
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