MC68HC705JP7 Datasheet, PDF (98/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
7.4.8 PB6/SDI Logic
The PB6/SDI pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-11. The operations of
PB6/SDI pin are summarized in Table 7-3.
READ $0005
SERIAL DATA IN (SDI)
SERIAL ENABLE (SPE)
WRITE $0005
DATA DIRECTION
REGISTER B
BIT DDRB6
R
WRITE $0001
READ $0001
WRITE $0011
RESET
PORT B DATA
REGISTER
BIT PB6
PULLDOWN
REGISTER B
R
BIT PDIB6
MASK OPTION REG. ($1FF1)
Figure 7-11. PB6/SDI Pin I/O Circuit
PB6
SDI
PULLDOWN
DEVICE
When using the PB6/SDI pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must
be set. This causes the PB6/SDI pin buffer to be disabled to allow
the PB6/SDI pin to act as an input that feeds the serial data input
(SDI) of the SIOP. The pulldown device is disabled in this case.
2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6
and PB6 data register bits are still accessible to the CPU and can
be altered or read without affecting the SIOP functionality.
However, if the DDRB6 bit is cleared, reading the PB6 data
register will return the current state of the PB6/SDI pin.
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Parallel Input/Output
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