MC68HC705JP7 Datasheet, PDF (91/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
Port B
7.4.2 Data Direction Register B
The contents of the port B data direction register (DDRB) determine
whether each port B pin is an input or an output. Writing a logic 1 to a
DDRB bit enables the output buffer for the associated port B pin. A
DDRB bit set to a logic 1 also disables the pulldown device for that pin.
Writing a logic 0 to a DDRB bit disables the output buffer for the
associated port B pin. A reset initializes all DDRB bits to logic 0s,
configuring all port B pins as inputs.
Address: $0005
Bit 7
6
5
4
3
2
1
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
Write:
Reset: 0
0
0
0
0
0
0
Figure 7-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears the
bits DDRB7–DDRB0.
1 = Corresponding port B pin configured as output and pulldown
device disabled
0 = Corresponding port B pin configured as input
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Parallel Input/Output
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