MC68HC705JP7 Datasheet, PDF (141/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
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Section 9. Simple Synchronous Serial Interface
9.1 Contents
9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.3 SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.3.2 Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.3.3 Serial Data Output (SDO). . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.4 SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
9.4.1 SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . 145
9.4.2 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
9.4.3 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
9.2 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to
provide efficient serial communications with peripheral devices or other
MCUs. SIOP is implemented as a 3-wire master/slave system with serial
clock (SCK), serial data input (SDI), and serial data output (SDO). A
block diagram of the SIOP is shown in Figure 9-1.
The SIOP subsystem shares its input/output pins with port B. When the
SIOP is enabled (SPE bit set in the SCR), the port B data direction and
data registers are bypassed by the SIOP. The port B data direction and
data registers will remain accessible and can be altered by the
application software, but these actions will not affect the SIOP
transmitted or received data.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Simple Synchronous Serial Interface
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141