MC68HC705JP7 Datasheet, PDF (186/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

EPROM/OTPROM
Freescale Semiconductor, Inc.
6. Port A external interrupt function (enable or disable)
7. IRQ trigger sensitivity (edge-triggered only or both edge- and
level-triggered)
8. COP watchdog (enable or disable)
Address:
Read:
Write:
Reset:
Erased:
$1FF1
Bit 7
6
5
4
3
2
1
SWPDI DELAY OSCRES SWAIT LVREN PIRQ LEVEL
Unaffected by reset
0
0
0
0
0
0
0
Figure 13-2. Mask Option Register (MOR)
Bit 0
COPEN
0
SWPDI — Software Pulldown Inhibit Bit
This EPROM bit inhibits software control of the port A and port B
pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
DELAY — Stop Startup Delay Bit
This EPROM bit selects the number of bus cycles that must elapse
before bus activity begins following a restart from the stop mode.
1 = Startup delay is 4064 bus cycles.
0 = Startup delay is 16 bus cycles.
CAUTION:
The 16-cycle delay option will work properly in devices with the internal
low-power oscillator or with a steady external clock source. Check
crystal/ceramic resonator specifications carefully before using the
16-cycle delay option with a crystal or ceramic resonator.
OSCRES — Oscillator Resistor Bit
This EPROM bit configures the internal shunt resistor.
1 = Oscillator configured with 2 M¾ shunt resistor
0 = Oscillator configured without a shunt resistor
Advance Information
186
MC68HC705JJ7 • MC68HC705JP7 — REV 4
EPROM/OTPROM
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