MC68HC705JP7 Datasheet, PDF (93/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
Port B
7.4.5 PB0, PBI, PB2, and PB3 Logic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and
PB3 pins of port B. When these port B pins are programmed as an
output, reading the port bit actually reads the value of the data latch and
not the voltage on the pin itself. When these port B pins are programmed
as an input, reading the port bit reads the voltage level on the pin. The
data latch can always be written, regardless of the state of its DDRB bit.
The operations of the PB0–PB3 pins are summarized in Table 7-2.
READ $0005
WRITE $0005
WRITE $0001
READ $0001
WRITE $0011
RESET
DATA DIRECTION
REGISTER B
R
BIT DDRBx
PORT BDATA
REGISTER
BIT PBx
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
(PINS PB0, PB1, PB2, PB3)
PBx
PULLDOWN
REGISTER B
R
BIT PDIBx
MASK OPTION REG. ($1FF1)
Figure 7-8. PB0–PB3 Pin I/O Circuit
PULLDOWN
DEVICE
The PB0–PB3 pins share their inputs with another module. When using
the other attached module, these conditions must be observed:
1. If the DDRB configures the pin as an output, then the port data
register can provide an output which may conflict with any external
input source to the other module. The pulldown device will be
disabled in this case.
2. If the DDRB configures the pin as an input, then reading the port
data register will return the state of the input in terms of the digital
threshold for that pin (analog inputs will default to logic states).
3. If DDRB configures the pin as an input and the pulldown device is
activated for a pin, it will also load the input to the other module.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Parallel Input/Output
For More Information On This Product,
Go to: www.freescale.com
Advance Information
93