MC68HC705JP7 Datasheet, PDF (55/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Software Interrupt
4.5 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.6 External Interrupts
These sources can generate external interrupts:
• IRQ/V_PP pin
• PA3–PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables these external
interrupts.
4.6.1 IRQ/V_PP Pin
An interrupt signal on the IRQ/V_PP pin latches an external interrupt
request. To help clean up slow edges, the input from the IRQ/V_PP pin is
processed by a Schmitt trigger gate. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU
then tests the I bit in the condition code register and the IRQE bit in the
IRQ status and control register (ISCR). If the I bit is clear and the IRQE
bit is set, then the CPU begins the interrupt sequence. The CPU clears
the IRQ latch while it fetches the interrupt vector, so that another external
interrupt request can be latched during the interrupt service routine. As
soon as the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-3 shows the logic for
external interrupts.
NOTE:
If the IRQ/V_PP pin is not in use, it should be connected to the V_DD pin.
The IRQ/V_PP pin can be negative edge-triggered only or negative edge-
and low level-triggered. External interrupt sensitivity is programmed with
the LEVEL bit in the mask option register (MOR).
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Interrupts
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