MC68HC705JP7 Datasheet, PDF (167/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Timer
Output Compare Registers
The result obtained by an input capture will be one count higher than the
value of the free-running timer counter preceding the external transition.
This delay is required for internal synchronization. Resolution is affected
by the prescaler, allowing the free-running timer counter to increment
once every four internal clock cycles (eight oscillator clock cycles).
Reading the ICRH inhibits future captures until the ICRL is also read.
Reading the ICRL after reading the timer status register (TSR) clears the
ICF flag bit. There is no conflict between reading the ICRL and transfers
from the free-running timer counters. The input capture registers always
contain the free-running timer counter value which corresponds to the
most recent input capture.
NOTE:
To prevent interrupts from occurring between readings of the ICRH and
ICRL, set the I bit in the condition code register (CCR) before reading
ICRH and clear the I bit after reading ICRL.
11.6 Output Compare Registers
The output compare function is a means of generating an output signal
when the 16-bit timer counter reaches a selected value as shown in
Figure 11-8. Software writes the selected value into the output compare
registers. On every fourth internal clock cycle (every eight oscillator
clock cycles) the output compare circuitry compares the value of the
free-running timer counter to the value written in the output compare
registers. When a match occurs, the timer transfers the output level
(OLVL) from the timer control register (TCR) to the PB4/AN4/TCMP pin.
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration
or a pulse train of specific frequency and duty cycle on the
PB4/AN4/TCMP pin.
The planned action on the PB4/AN4/TCMP pin depends on the value
stored in the OLVL bit in the TCR, and it occurs when the value of the
16-bit free-running timer counter matches the value in the output
compare registers shown in Figure 11-9. These registers are read/write
bits and are unaffected by reset.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Programmable Timer
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