MC68HC705JP7 Datasheet, PDF (67/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets
Power-On Reset
5.3 Power-On Reset
A positive transition on the V_DD pin generates a power-on reset. The
power-on reset is strictly for conditions during powering up and cannot
be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (t_cyc) after the oscillator
becomes active allows the clock generator to stabilize. If the RESET pin
is at logic 0 at the end of this multiple t_cyc time, the MCU remains in the
reset condition until the signal on the RESET pin goes to a logic 1.
5.4 External Reset
A logic 0 applied to the RESET pin for a minimum of one and one half
t_cyc generates an external reset. This pin is connected to a Schmitt
trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. The external reset
occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold.
This active low input will generate the internal RST signal that resets the
CPU and peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown
device that is activated by three internal reset sources. This reset
pulldown device will only be asserted for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
NOTE:
Do not connect the RESET pin directly to V_DD, as this may overload
some power supply designs if the internal pulldown on the RESET pin
should activate. If an external reset function is not required, the RESET
pin should be left unconnected.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
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