MC68HC705JP7 Datasheet, PDF (145/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Simple Synchronous Serial Interface
SIOP Registers
The first data bit will be shifted out to the SDO pin on the first falling edge
of the SCK. The remaining data bits will be shifted out to the SDI pin on
subsequent falling edges of SCK. The SDO pin will present valid data at
least 100 nanoseconds before the rising edge of the SCK and remain
valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
9.4 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register
(SCR) located at address $000A, the SIOP status register (SSR) located
at address $000B, and the SIOP data register (SDR) located at address
$000C.
9.4.1 SIOP Control Register (SCR)
The SIOP control register (SCR) is located at address $000A and
contains seven control bits and a write-only reset of the interrupt flag.
Figure 9-4 shows the position of each bit in the register and indicates the
value of each bit after reset.
Address: $000A
Bit 7
6
5
4
3
2
1
Read:
0
SPIE
SPE
LSBF MSTR
CPHA SPR1
Write:
SPIR
Reset: 0
0
0
0
0
0
0
Figure 9-4. SIOP Control Register (SCR)
Bit 0
SPR0
0
SPIE — Serial Peripheral Interrupt Enable Bit
The SPIE bit enables the SIOP to generate an interrupt whenever the
SPIF flag bit in the SSR is set. Clearing the SPIE bit will not affect the
state of the SPIF flag bit and will not terminate a serial interrupt once
the interrupt sequence has started. Reset clears the SPIE bit.
1 = Serial interrupt enabled
0 = Serial interrupt disabled
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Simple Synchronous Serial Interface
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