MC68HC705JP7 Datasheet, PDF (79/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

6.4.1 Stop Mode
Freescale Semiconductor, Inc.
Operating Modes
Low-Power Modes
The STOP instruction puts the MCU in a mode with the lowest power
consumption and affects the MCU as follows:
• Turns off the central processor unit (CPU) clock and all internal
clocks by stopping both the external pin oscillator and the internal
low-power oscillator. The selection of the oscillator by the OM1
and OM2 bits in the ISCR is not affected. The stopped clocks turn
off the COP watchdog, the core timer, the programmable timer,
the analog subsystem, and the SIOP.
• Removes any pending core timer interrupts by clearing the core
timer interrupt flags (CTOF and RTIF) in the core timer status and
control register (CTSCR)
• Disables any further core timer interrupts by clearing the core
timer interrupt enable bits (CTOFE and RTIE) in the CTSCR
• Removes any pending programmable timer interrupts by clearing
the timer interrupt flags (ICF, OCF, and TOF) in the timer status
register (TSR)
• Disables any further programmable timer interrupts by clearing the
timer interrupt enable bits (ICIE, OCIE, and TOIE) in the timer
control register (TCR)
• Enables external interrupts via the IRQ/V_PP pin by setting the
IRQE bit in the IRQ status and control register (ISCR). External
interrupts are also enabled via the PA0 through PA3 pins, if the
port A interrupts are enabled by the PIRQ bit in the mask option
register (MOR).
• Enables interrupts in general by clearing the I bit in the condition
code register
The STOP instruction does not affect any other bits, registers, or I/O
lines.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Operating Modes
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