MC68HC705JP7 Datasheet, PDF (97/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
Port B
SERIAL DATA OUT (SDO)
SERIAL ENABLE (SPE)
V_DD
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER B
R
BIT DDRB5
WRITE $0001
READ $0001
WRITE $0011
RESET
PORT B DATA
REGISTER
BIT PB5
PULLDOWN
REGISTER B
R
BIT PDIB5
MASK OPTION REG. ($1FF1)
Figure 7-10. PB5/SDO Pin I/O Circuit
PB5
SDO
PULLDOWN
DEVICE
3. If the SIOP function is terminated by clearing the SPE bit in the
SCR, then the last conditions stored in the DDRB5, PDIB5, and
PB5 register bits will then control the PB5/SDO pin.
4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in
the SCR and the DDRB5 bit must be cleared. Depending on the
external application, the pulldown device may also be disabled by
setting the PDIB5 pulldown inhibit bit.
5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the
SCR must be cleared and the PDIB5 bit must be set. The pulldown
device will be disabled in this case.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Parallel Input/Output
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