MC68HC705JP7 Datasheet, PDF (96/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
.
Table 7-2. Port B Pin Functions — PB0–PB4
Control Bits
Port B
Pin
Comparator 1
Timer _SWPDI
CMP1 COE1 OPT in COPR OLVL ^{in MOR}
Port B
PORTB Access
(Pin or Data
Register)
Result on
Port B Pins
PDIBx _DDRBx⁽¹⁾ Read Write Pulldown Pin
0
0
0
Pin Data
On PBx in
PB0
PB1
PB2
X⁽²⁾
X⁽²⁾
X⁽²⁾
0
1
0
X⁽²⁾
1
X⁽²⁾
0
Pin Data
Pin Data
Off PBx in
Off PBx in
PB3
X⁽²⁾
X⁽²⁾
1
Data Data
Off PBx out
0
0
0
Pin Data
On PB4 in
X⁽²⁾ X⁽²⁾
X⁽²⁾
X⁽²⁾
0
1
0
Pin Data
Off PB4 in
1
X⁽²⁾
0
Pin Data
Off PB4 in
X⁽²⁾ X⁽²⁾
0
PB4 _X(2)
0
1
0
X⁽²⁾
X⁽²⁾
1
Data Data
Off PB4 out
0
X⁽²⁾
X⁽²⁾
1
Data Data
Off PB4 out
0
1
1
0
X⁽²⁾
X⁽²⁾
1
Data Data
Off PB4 out
X⁽²⁾ X⁽²⁾
X⁽²⁾
1
X⁽²⁾
X⁽²⁾
1
1
Data
Off
1
1
1
1
X⁽²⁾
X⁽²⁾
X⁽²⁾
1
1
Data
Off
1
1. DDRB can always be read or written.
2. Don’t care
7.4.7 PB5/SDO Logic
The PB5/SDO pin can be used as a simple I/O port pin or be controlled
by the SIOP serial interface as shown in Figure 7-10. The operations of
the PB5 pin are summarized in Table 7-3.
When using the PB5/SDO pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must
be set. This causes the PB5/SDO pin buffer to be enabled and to
be driven by the serial data output (SDO) from the SIOP. The
pulldown device will be disabled in this case.
2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5
and PB5 data register bits are still accessible to the CPU and can
be altered or read without affecting the SIOP functionality.
However, if the DDRB5 bit is cleared, reading the PB5 data
register will return the current state of the PB5/SDO pin.
Advance Information
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Parallel Input/Output
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