MC68HC705JP7 Datasheet, PDF (110/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog Subsystem
The end of the A/D conversion time can be captured by these means:
• Input capture in the 16-bit programmable timer
• Interrupt generated by the comparator output
• Software polling of the comparator output using software loop time
8.3 Analog Multiplex Register
The analog multiplex register (AMUX) controls the general
interconnection and operation. The control bits in the AMUX are shown
in Figure 8-2.
Address: $0003
Bit 7
6
5
4
3
2
1
Read:
HOLD DHOLD INV
Write:
VREF MUX4 MUX3 MUX2
Reset: 1
0
0
0
0
0
0
Figure 8-2. Analog Multiplex Register (AMUX)
Bit 0
MUX1
0
HOLD, DHOLD
These read/write bits control the source connection to the negative
input of voltage comparator 2 shown in Figure 8-3. This allows the
voltage on the internal temperature sensing diode, the channel
selection bus, or the divide-by-two channel selection bus to charge
the internal sample capacitor and to also be presented to comparator
2. The decoding of these sources is given in Table 8-1.
During the hold case when both the HOLD and DHOLD bits are clear,
the VOFF bit in the analog status register (ASR) can offset the V_SS
reference on the sample capacitor by approximately 100 mV. This
offset source is bypassed whenever the sample capacitor is being
charged with either the HOLD or DHOLD bit set. The VOFF bit must
be enabled by the OPT bit in the COPR at location $1FF0.
Advance Information
110
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Analog Subsystem
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