MC68HC705JP7 Datasheet, PDF (113/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog Subsystem
Analog Multiplex Register
RISE
V+
WHEN
V+ > V–
V+
RISE
WHEN
V+ > V–
VIO +
COMP
–
VIO +
COMP
–
V–
V–
INV = 0
INV = 1
Figure 8-4. INV Bit Action
NOTE:
Either comparator may generate an output flag when the inputs are
exchanged due to a change in the state of the INV bit. It is therefore
recommended that the INV bit not be changed while waiting for a
comparator flag. Further, any changes to the state of the INV bit should
be followed by writing a logic 1 to both the CPFR1 and CPFR2 bits to
clear any extraneous CPF1 or CPF2 flags that may have occurred.
VREF
This read/write bit connects the channel select bus to V_DD for making
a reference voltage measurement. It cannot be selected if any of the
other input sources to the channel select bus are selected as shown
in Table 8-2. This bit is cleared by a reset of the device.
1 = Channel select bus connected to V_DD if all MUX1:4 are cleared.
0 = Channel select bus cannot be connected to V_DD.
MUX1:4
These are read/write bits that connect the analog subsystem pins to
the channel select bus and voltage comparator 2 for purposes of
making a voltage measurement. They can be selected individually or
combined with any of the other input sources to the channel select
bus as shown in Table 8-2.
NOTE:
The V_AOFF voltage source shown in Figure 8-1 depicts a small offset
voltage generated by the total chip current passing through the package
bond wires and lead frame that are attached to the single V_SS pin. This
offset raises the internal V_SS reference (AV_SS) in the analog subsystem
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Analog Subsystem
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