MC68HC705JP7 Datasheet, PDF (69/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets
Internal Resets
Address: $1FF0
Bit 7
6
5
4
3
2
1
Read:
EPMSEC OPT
Write:
Reset:
U
U
U
U
U
U
U
= Unimplemented U = Unaffected
Figure 5-2. COP and Security Register (COPR)
Bit 0
COPC
U
EPMSEC — EPROM Security⁽¹⁾ Bit
The EPMSEC bit is an EPROM, write-only security bit to protect the
contents of the user EPROM code stored in locations $0700–$1FFF.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by
comparator 1 output to PB4 and voltage offset capability to sample
capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
NOTE: See 8.8.1 Voltage Comparator 1 and 8.11 Sample and Hold for further
descriptions of the OPT bit.
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
The COP watchdog reset will assert the pulldown device to pull the
RESET pin low for three to four cycles of the internal bus.
The COP watchdog reset function can be enabled or disabled by
programming the COPEN bit in the MOR.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the EPROM/OTPROM difficult for unauthorized users.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Resets
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Advance Information
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