MC68HC705JP7 Datasheet, PDF (58/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
Freescale Semiconductor, Inc.
IRQ/V_PP pin and other PA0:3 pins are to be ignored until ALL of the
PA0:3 pins have returned to a low level. Similarly, if the IRQ/V_PP pin is
at a low level, the PA0:3 pins will be ignored until the IRQ/V_PP pin returns
to a high state.
4.6.3 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4,
contains an external interrupt mask (IRQE), an external interrupt flag
(IRQF), and a flag reset bit (IRQR). Unused bits will read as logic 0s. The
ISCR also contains two control bits for the oscillators, external pin
oscillator, and internal low-power oscillator. Reset sets the IRQE and
OM2 bits and clears all the other bits.
Address: $000D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
IRQF
0
0
0
IRQE OM2 OM1
Write:
R
IRQR
Reset: 1
1
0
0
0
0
U
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 4-4. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
OM1 and OM2 — Oscillator Select Bits
These bits control the selection and enabling of the oscillator source
for the MCU. One choice is the internal low-power oscillator (LPO).
The other choice is the external pin oscillator (EPO) which is common
to most M68HC05 MCU devices. The EPO uses external components
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Interrupts
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