MC68HC705JP7 Datasheet, PDF (137/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog Subsystem
Voltage Comparator Features
voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture
interrupts.
The output of comparator 1 can be connected to the port logic driving the
PB4/AN4/TCMP/CMP1 pin such that the output of the comparator is
ORed with the PB4 data bit and the OLVL bit from the 16-bit timer. This
capability requires that the OPT bit is set in the COPR at location $1FF0
as in Figure 8-12, and the COE1 bit is set in the ASR at location $001E.
Address: $1FF0
Bit 7
6
5
4
3
2
1
Read:
EPMSEC OPT
Write:
Reset:
U
U
U
U
U
U
U
= Unimplemented U = Unaffected
Figure 8-12. COP and Security Register (COPR)
Bit 0
COPC
U
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by
comparator 1 output to PB4 and voltage offset capability to sample
capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
8.8.2 Voltage Comparator 2
Voltage comparator 2 can be used as a simple comparator if its charge
current source and discharge device are disabled by clearing the ISEN
bit in the ACR. If the ISEN bit is set, the internal ramp discharge device
connected to PB0/AN0 may become active and try to pull down any
voltage source that may be connected to that pin. Also, since voltage
comparator 2 is always connected to two of the port B I/O pins, these
pins should be configured as inputs and have their software
programmable pulldowns disabled.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Analog Subsystem
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