MC68HC705JP7 Datasheet, PDF (147/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Simple Synchronous Serial Interface
SIOP Registers
SPIR — Serial Peripheral Interrupt Reset Bit
The SPIR bit is a write-only control to reset the SPIF flag bit in the
SSR. Reading the SPIR bit will return a logic 0.
1 = Reset the SPIF flag bit
0 = No effect
CPHA — Clock Phase Bit
The CPHA bit controls the clock timing and phase in the SIOP. Data
is changed on the falling edge of SCK and data is captured (read) on
the rising edge of SCK. This bit is cleared by reset.
1 = SCK is idle low
0 = SCK is idle high
SPR0:1 — Serial Peripheral Clock Rate Select Bits
The SPR0 and SPR1 bits select one of four clock rates given in
Table 9-1 to be supplied on the PB7/SCK pin when the device is
configured with the SIOP as a master (MSTR = 1). The fastest rate is
when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits
are cleared by reset, which places the SIOP clock selection at the
slowest rate.
Table 9-1. SIOP Clock Rate Selection
SPR1
0
0
1
1
SPR0
0
1
0
1
SIOP Clock Rate
Oscillator Frequency
Divided by:
64
32
16
8
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Simple Synchronous Serial Interface
For More Information On This Product,
Go to: www.freescale.com
Advance Information
147