MC68HC705JP7 Datasheet, PDF (52/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Interrupts
Freescale Semiconductor, Inc.
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3 Interrupt Vectors
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
actually interrupt a lower priority interrupt service routine unless the
lower priority interrupt service routine clears the I bit.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
MOR
Control
Bit
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-on logic
RESET pin
Low-voltage reset
—
—
—
Illegal address reset
1
$1FFE–$1FFF
COP watchdog
COPEN⁽¹⁾
Software
interrupt (SWI)
User code
—
—
—
Same priority
as instruction
$1FFC–$1FFD
IRQ/V_PP pin
—
External
interrupt (IRQ)
PA3 pin
PA2 pin
PA1 pin
PA0 pin
I bit
IRQE bit
2
$1FFA–$1FFB
PIRQ⁽²⁾
Core timer
interrupts
TOF bit
RTIF bit
—
I bit
TOFE bit
RTIE bit
3
$1FF8–$1FF9
Programmable
timer interrupts
ICF bit
OCF bit
TOF bit
ICIE bit
—
I bit
OCIE bit
4
$1FF6–$1FF7
TOIE bit
Serial interrupt SPIF bit
—
I bit
SPIE bit
5
$1FF4–$1FF5
Analog interrupt
CPF1 bit
CPF2 bit
—
I bit
CPIE bit
6
$1FF2–$1FF3
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Interrupts
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