MC68HC705JP7 Datasheet, PDF (89/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
Port A
7.3.5 Port A Logic
When a PA0:PA5 pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a PA0:PA5 pin is programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be
written, regardless of the state of its DDR bit. Figure 7-4 shows the I/O
logic of PA0–PA5 pins of port A.
The data latch can always be written, regardless of the state of its DDR
bits. Table 7-1 summarizes the operations of the port A pins.
READ $0004
WRITE $0004
WRITE $0000
READ $0000
WRITE $0010
RESET
DATA DIRECTION
REGISTER A
R
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
EXTERNAL
INTERRUPT
REQUEST
(PA0:3)
PAx
HIGH SINK/SOURCE
CURRENT
CAPABILITY
PULLDOWN
REGISTER A
BIT PDIAx
R
MASK OPTION REG. ($1FF1)
Figure 7-4. Port A I/O Circuit
PULLDOWN
DEVICE
Table 7-1. Port A Pin Functions
Port A
Pin(s)
SWPDI
(in MOR)
Port A
PDIAx
DDRAx⁽¹⁾
PORTA Access
(Pin or Data Register)
Read
Write
PA0
0
0
PA1
PA2
0
1
PA3
1
X
PA4
PA5
X⁽²⁾
X⁽²⁾
0
Pin
Data
0
Pin
Data
0
Pin
Data
1
Data
Data
1. DDRA can always be read or written.
2. Don’t care
Result on
Port A Pins
Pulldown
Pin
On
PAx in
Off
PAx in
Off
PAx in
Off
PAx out
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Parallel Input/Output
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