MC68HC705JP7 Datasheet, PDF (70/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Resets
Freescale Semiconductor, Inc.
5.5.3 Low-Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the
voltage on the V_DD pin falls below the LVR trip voltage. The LVR will
assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
The LVR reset function can be enabled or disabled by programming the
LVREN bit in the MOR.
NOTE: The LVR is intended for applications where the V_DD supply voltage
normally operates above 4.5 volts.
5.5.4 Illegal Address Reset
An opcode fetch (execution of an instruction) at an address that is not in
the EPROM (locations $0700–$1FFF) or the RAM (locations
$0020–$00FF) generates an illegal address reset. The illegal address
reset will assert the pulldown device to pull the RESET pin low for three
to four cycles of the internal bus.
5.6 Reset States
This subsection describe how the various resets initialize the MCU.
5.6.1 CPU
A reset has these effects on the CPU:
• Loads the stack pointer with $FF
• Sets the I bit in the condition code register, inhibiting interrupts
• Loads the program counter with the user-defined reset vector from
locations $1FFE and $1FFF
• Clears the stop latch, enabling the CPU clock
• Clears the wait latch, bringing the CPU out of the wait mode
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Resets
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