MC68HC705JP7 Datasheet, PDF (144/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Simple Synchronous Serial Interface
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
SDO
SCK (IDLE = 0)
(CPHA = 1)
100 ns
100 ns
SDI
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
Figure 9-3. SIOP Timing Diagram (CPHA = 1)
The only difference in the master and slave modes of operation is the
sourcing of the SCK. In master mode, SCK is driven from an internal
source within the MCU. In slave mode, SCK is driven from a source
external to the MCU. The SCK frequency is based on one of four
divisions of the oscillator clock that is selected by the SPR0 and SPR1
bits in the SCR.
9.3.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is
enabled. New data is presented to the SDI pin on the falling edge of
SCK. Valid data must be present at least 100 nanoseconds before the
rising edge of SCK and remain valid for 100 nanoseconds after the rising
edge of SCK. See Figure 9-3.
9.3.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is
enabled. The state of the PB5/SDO pin reflects the value of the first bit
received on the previous transmission. Prior to enabling the SIOP, the
PB5/SDO can be initialized to determine the beginning state. While
SIOP is enabled, the port B logic cannot be used as a standard output
since that pin is connected to the last stage of the SIOP serial shift
register. A control bit (LSBF) is included in the SCR to allow the data to
be transmitted in either the MSB first format or the LSB first format.
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MC68HC705JJ7 • MC68HC705JP7 — REV 4
Simple Synchronous Serial Interface
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