MC68HC705JP7 Datasheet, PDF (59/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
External Interrupts
like filter capacitors and a crystal or ceramic resonator and consumes
more power. The selection and enable conditions for these two
oscillators are shown in Table 4-2.
Table 4-2. Oscillator Selection
OM2 OM1
Oscillator
Selected
by CPU
0
0
Internal
0
1
External
1
0
Internal
1
1
Internal
Internal
Low-Power
Oscillator
(LPO)
Enabled
Disabled
Enabled
Enabled
External
Pin
Oscillator
(EPO)
Disabled
Enabled
Disabled
Enabled
Power
Consumption
Lowest
Normal
Lowest
Normal
Therefore, the lowest power is consumed when OM1 is cleared. The
state with both OM1 and OM2 set is provided so that the EPO can be
started and allowed to stabilize while the LPO still clocks the MCU.
The reset state is for OM1 to be cleared and OM2 to be set, which
selects the LPO and disables the EPO.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external
interrupt request is pending. Writing to the IRQF bit has no effect.
Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
The following conditions set the IRQ flag:
• An external interrupt signal on the IRQ/V_PP pin
• An external interrupt signal on pin PA0, PA1, PA2, or PA3
when the PA0–PA3 pins are enabled by the PIRQ bit in the MOR
to serve as external interrupt sources.
The following conditions clear the IRQ flag:
• When the CPU fetches the interrupt vector
• When a logic 1 is written to the IRQR bit
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Interrupts
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