MC68HC705JP7 Datasheet, PDF (155/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Core Timer
Core Timer Counter Register
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
TOF = 1/(f_OSC ÷ 2¹¹)
(Microseconds)
RTI
Rate
RT1 RT0 = f_OSC
@ f_OSC (MHz)
divided
by:
4.2 2.0 1.0
MHz MHz MHz
Real-Time
Interrupt Period
(RTI)
(Milliseconds)
@ f_OSC (MHz)
4.2 2.0 1.0
MHz MHz MHz
00
01
488 1024 2048
10
11
2^{15 7.80 16.4 32.8}
2^{16 15.6 32.8 65.5}
2^{17 31.2 65.5 131}
2^{18 62.4 131 262}
COP Timeout Period
COP = 7-to-8 RTI Periods
(Milliseconds)
@ f_OSC (MHz)
4.2 MHz
2.0 MHz
1.0 MHz
Min Max Min Max Min Max
54.6 62.4 115 131 229 262
109 125 229 262 459 524
218 250 459 524 918 1049
437 499 918 1049 1835 2097
10.4 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the
basis of the core timer. The value of the first eight stages is readable at
any time from the read-only timer counter register as shown in
Figure 10-3.
Address: $0009
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-3. Core Timer Counter Register (CTCR)
Power-on clears the entire counter chain and begins clocking the
counter. After the startup delay (16 or 4064 internal bus cycles
depending on the DELAY bit in the mask option register (MOR)), the
power-on reset circuit is released, clearing the counter again and
allowing the MCU to come out of reset.
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Core Timer
For More Information On This Product,
Go to: www.freescale.com
Advance Information
155