MC68HC705JP7 Datasheet, PDF (86/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output
7.3.2 Data Direction Register A
The contents of the port A data direction register (DDRA) determine
whether each port A pin is an input or an output. Writing a logic 1 to a
DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic 1 also disables the pulldown device for that pin.
Writing a logic 0 to a DDRA bit disables the output buffer for the
associated port A pin. The upper two bits always read as logic 0s. A reset
initializes all DDRA bits to logic 0s, configuring all port A pins as inputs
and disabling the voltage comparators from driving PA4 or PA5.
Address: $0004
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA)
DDRA5–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears the
DDRA5–DDRA0 bits.
1 = Corresponding port A pin configured as output and pulldown
device disabled
0 = Corresponding port A pin configured as input
Advance Information
86
MC68HC705JJ7 • MC68HC705JP7 — REV 4
Parallel Input/Output
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA