MC68HC705JP7 Datasheet, PDF (163/242 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Timer
Alternate Counter Registers
Address: $0018
Bit 7
6
5
4
3
2
Read: Bit 15
14
13
12
11
10
Write:
Reset: 1
1
1
1
1
1
1
Bit 0
9
Bit 8
1
1
Address: $0018
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 1
1
1
1
1
1
0
0
= Unimplemented
Figure 11-3. Programmable Timer Registers (TMRH and TMRL)
When the free-running counter rolls over from $FFFF to $0000, the timer
overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can
generate an interrupt if the timer overflow interrupt enable bit (TOIE) is
also set in the TCR. The TOF flag bit can only be reset by reading the
TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and
TMRL in any order or any number of times does not have any effect on
the 16-bit free-running counter.
NOTE:
To prevent interrupts from occurring between readings of the TMRH and
TMRL, set the I bit in the condition code register (CCR) before reading
TMRH and clear the I bit after reading TMRL.
11.4 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and
alternate counter registers is shown in Figure 11-4. The alternate
counter registers behave the same as the timer registers, except that
any reads of the alternate counter will not have any effect on the TOF
MC68HC705JJ7 • MC68HC705JP7 — REV 4
MOTOROLA
Programmable Timer
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