PIC18F6585 Datasheet, PDF (94/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
5.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
5.5.4
PROTECTION AGAINST SPURIOUS
WRITES
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 24.0 “Special Features of the
CPU” for more detail.
5.6 Flash Program Operation During
Code Protection
See Section 24.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
TABLE 5-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)
TABLAT Program Memory Table Latch
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF
RBIF
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1 EEPGD CFGS
—
FREE WRERR WREN
WR
RD
IPR2
—
CMIP
—
EEIP BCLIP LVDIP TMR3IP CCP2IP
PIR2
—
CMIF
—
EEIF BCLIF LVDIF TMR3IF CCP2IF
PIE2
—
CMIE
—
EEIE BCLIE LVDIE TMR3IE CCP2IE
Legend: x = unknown, u = unchanged, r = reserved, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
--00 0000 --00 0000
0000 0000
0000 0000
0000 0000
0000 0000
—
xx-0 x000
-1-1 1111
-0-0 0000
-0-0 0000
0000 0000
0000 0000
0000 0000
0000 0000
—
uu-0 u000
-1-1 1111
-0-0 0000
-0-0 0000
DS30491C-page 92
 2004 Microchip Technology Inc.