PIC18F6585 Datasheet, PDF (282/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
REGISTER 23-2: CANSTAT: CAN STATUS REGISTER (CONTINUED)
bit 4-0
Mode 1,2:
EICODE4:EICODE0: Interrupt Code bits in Mode 1 and Mode 2
When an interrupt occurs, a prioritized coded interrupt value will be present in these bits. This
code indicates the source of the interrupt. Unlike ICODE bits in Mode 0, these bits may not be
copied directly to EWIN bits to map interrupted buffer to Access Bank area. If required, user
software may maintain a table in program memory to map EICODE bits to EWIN bits and access
interrupt buffer in Access Bank area.
EICODE4:EICODE0 Value
No interrupt
00000
Error interrupt
00010
TXB2 interrupt
00100
TXB1 interrupt
00110
TXB0 interrupt
RXB1 interrupt
01000
10001/10000⁽²⁾
RXB0 interrupt
10000
Wake-up interrupt
RX/TX B0 interrupt
RX/TX B1 interrupt
RX/TX B2 interrupt
RX/TX B3 interrupt
RX/TX B4 interrupt
RX/TX B4 interrupt
01110
10010⁽²⁾
10011⁽²⁾
10100⁽²⁾
10101⁽²⁾
10110⁽²⁾
10111⁽²⁾
Note 1: To achieve maximum power saving and/or able to wake-up on CAN bus activity,
switch CAN module to Disable mode before putting the device to Sleep.
2: In Mode 2, if the buffer is configured as a receiver, EICODE bits will always contain
‘10000’ upon interrupt.
Legend:
C = Clearable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit W = Writable bit
‘0’ = Bit is cleared
- n = Value at POR
x = Bit is unknown
DS30491C-page 280
 2004 Microchip Technology Inc.