PIC18F6585 Datasheet, PDF (144/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 6-bit wide port with 5 bidirectional pins and
1 unidirectional pin. The corresponding data direction
register is TRISG. Setting a TRISG bit (= 1) will make
the corresponding PORTG pin an input (i.e., put the
corresponding output driver in a high-impedance
mode). Clearing a TRISG bit (= 0) will make the corre-
sponding PORTG pin an output (i.e., put the contents
of the output latch on the selected pin).
The Data Latch register (LATG) is also memory mapped.
Read-modify-write operations on the LATG register read
and write the latched output value for PORTG.
Pins RG0-RG2 on PORTG are multiplexed with the CAN
peripheral. Refer to Section 23.0 “ECAN Module” for
proper settings of TRISG when CAN is enabled. RG5 is
multiplexed with MCLR/VPP. Refer to Register 24-5 for
more information.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an output,
while other peripherals override the TRIS bit to make a
pin an input. The user should refer to the corresponding
peripheral section for the correct TRIS bit settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
EXAMPLE 10-7: INITIALIZING PORT
CLRF PORTG
CLRF LATG
MOVLW 04h
MOVWF TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
Note 1: On a Power-on Reset, RG5 is enabled as
a digital input only if Master Clear
functionality is disabled (MCLRE = 0).
2: If the device Master Clear is disabled,
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
(CONFIG4L<2> = 0); or
b) make certain that RB5/KBI1/PGM is
held low during entry into ICSP.
FIGURE 10-16: RG0/CANTX1 PIN BLOCK DIAGRAM
TXD
OPMODE2:OPMODE0 = 000
0
Data Bus
RD LATG
1
DQ
WR PORTG or
WR LATG
CK Q
Data Latch
DQ
ENDRHI
VDD
P
I/O pin
WR TRISG
RD TRISG
CK Q
TRIS Latch
N
VSS
OPMODE2:OPMODE0 = 000
QD
Schmitt
Trigger
RD PORTG
Note: I/O pins have diode protection to VDD and VSS.
ENEN
DS30491C-page 142
 2004 Microchip Technology Inc.