PIC18F6585 Datasheet, PDF (344/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
FIGURE 23-7:
ERROR MODES STATE DIAGRAM
Reset
RXERRCNT < 127 or
TXERRCNT < 127
Error-
Active
Error-
Passive
RXERRCNT > 127 or
TXERRCNT > 127
TXERRCNT > 255
Bus-
Off
128 occurrences of
11 consecutive
“recessive” bits
23.15 CAN Interrupts
The module has several sources of interrupts. Each of
these interrupts can be individually enabled or dis-
abled. The PIR3 register contains interrupt flags. The
PIE3 register contains the enables for the 8 main inter-
rupts. A special set of read-only bits in the CANSTAT
register, the ICODE bits, can be used in combination
with a jump table for efficient handling of interrupts.
All interrupts have one source with the exception of the
error interrupt and buffer interrupts in Mode 1 and 2. Any
of the error interrupt sources can set the error interrupt
flag. The source of the error interrupt can be determined
by reading the Communication Status register,
COMSTAT. In Mode 1 and 2, there are two interrupt
enable/disable and flag bits – one for all transmit buffers
and the other for all receive buffers.
The interrupts can be broken up into two categories:
receive and transmit interrupts.
The receive related interrupts are:
• Receive Interrupts
• Wake-up Interrupt
• Receiver Overrun Interrupt
• Receiver Warning Interrupt
• Receiver Error-Passive Interrupt
The transmit related interrupts are:
• Transmit Interrupts
• Transmitter Warning Interrupt
• Transmitter Error-Passive Interrupt
• Bus-Off Interrupt
23.15.1 INTERRUPT CODE BITS
To simplify the interrupt handling process in user firm-
ware, the ECAN module encodes a special set of bits. In
Mode 0, these bits are ICODE<2:0> in the CANSTAT
register. In Mode 1 and 2, these bits are EICODE<3:0>
in the CANSTAT register. Interrupts are internally priori-
tized such that the higher priority interrupts are assigned
lower values. Once the highest priority interrupt condi-
tion has been cleared, the code for the next highest
priority interrupt that is pending (if any) will be reflected
by the ICODE bits. Note that only those interrupt sources
that have their associated interrupt enable bit set will be
reflected in the ICODE bits.
In Mode 2, when a receive message interrupt occurs,
EICODE bits will always consist of ‘10000’. User
firmware may use FIFO pointer bits to actually access
the next available buffer.
DS30491C-page 342
 2004 Microchip Technology Inc.