PIC18F6585 Datasheet, PDF (45/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
RXM1EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM1SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXM1SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXM0SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXM0SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF5SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF5SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF4SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF4SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF3SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF3SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF2SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF1SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDL PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0SIDL PIC18F6X8X PIC18F8X8X
xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF0SIDH PIC18F6X8X PIC18F8X8X
xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.
7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.
 2004 Microchip Technology Inc.
DS30491C-page 43