PIC18F6585 Datasheet, PDF (133/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
10.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory mapped.
Read-modify-write operations on the LATC register read
and write the latched output value for PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register
without concern due to peripheral overrides.
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).
EXAMPLE 10-3: INITIALIZING PORTC
CLRF
CLRF
MOVLW
MOVWF
PORTC
LATC
0CFh
TRISC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 10-8:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTC/Peripheral Out Select
Peripheral Data Out
RD LATC
Data Bus
WR LATC or
WR PORTC
WR TRISC
RD TRISC
Peripheral Output
Enable⁽²⁾
D
Q
CK Q
Data Latch
D
Q
CK Q
TRIS Latch
RD PORTC
Peripheral Data In
0
VDD
P
1
N
TRIS
VSS
Override
Logic
Schmitt
Trigger
Q
D
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: Peripheral output enable is only active if peripheral select is active.
I/O pin⁽¹⁾
TRIS OVERRIDE
Pin Override
RC0
Yes
RC1
Yes
RC2
Yes
RC3
Yes
RC4
Yes
RC5
Yes
RC6
Yes
RC7
Yes
Peripheral
Timer1 Osc for
Timer1/Timer3
Timer1 Osc for
Timer1/Timer3,
CCP2 I/O
CCP1 I/O
SPI/I²C
Master Clock
I²C Data Out
SPI Data Out
USART Async
Xmit, Sync Clock
USART Sync
Data Out
 2004 Microchip Technology Inc.
DS30491C-page 131