PIC18F6585 Datasheet, PDF (432/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
TABLE 27-8: CLKO AND I/O TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TOSH2CKL OSC1 ↑ to CLKO ↓
—
75
200
ns
(1)
11
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
200
ns
(1)
12
TCKR
CLKO Rise Time
—
35
100
ns
(1)
13
TCKF
CLKO Fall Time
—
35
100
ns
(1)
14
TCKL2IOV CLKO ↓ to Port Out Valid
—
— 0.5 TCY + 20 ns
(1)
15
TIOV2CKH Port In Valid before CLKO ↑
0.25 TCY + 25 —
—
ns
(1)
16
TCKH2IOI Port In Hold after CLKO ↑
0
—
—
ns
(1)
17
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port PIC18FXX8X
18A
Input Invalid
PIC18LFXX8X
(I/O in hold time)
100
—
—
ns
200
—
—
ns
19
TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
—
ns
20
TIOR
Port Output Rise Time
PIC18FXX8X
—
10
25
ns
20A
PIC18LFXX8X
—
—
60
ns
21
TIOF
Port Output Fall Time
PIC18FXX8X
—
10
25
ns
21A
PIC18LFXX8X
—
—
60
ns
22†
TINP
INT pin High or Low Time
TCY
—
—
ns
23†
TRBP
RB7:RB4 Change INT High or Low Time
TCY
—
—
ns
24†
TRCP
RC7:RC4 Change INT High or Low Time
20
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 27-8:
PROGRAM MEMORY READ TIMING DIAGRAM
OSC1
A<19:16>
BA0
AD<15:0>
ALE
CE
OE
Q1
Q2
Q3
Q4
Q1
Address
Address
150
151
164
171
160
155
167
Data from External
163
162
161
166
168
169
171A
165
Q2
Address
Address
DS30491C-page 430
 2004 Microchip Technology Inc.