PIC18F6585 Datasheet, PDF (483/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
Product Identification System ........................................... 487
Program Counter
PCL, PCLATH and PCLATU
Registers............................................................. 56
Program Memory
Instructions.................................................................. 57
Two-Word ........................................................... 58
Interrupt Vector ........................................................... 51
Map and Stack for
PIC18F6585/8585............................................... 52
Map and Stack for
PIC18F6680/8680............................................... 52
Memory Access for
PIC18F8X8X Modes ........................................... 52
Memory Maps for
PIC18F8X8X Modes ........................................... 53
Reset Vector ............................................................... 51
Program Memory Modes
Extended Microcontroller ............................................ 93
Microcontroller ............................................................ 93
Microprocessor ........................................................... 93
Microprocessor with
Boot Block........................................................... 93
Program Memory Write Timing
Requirements............................................................ 432
Program Verification and
Code Protection ........................................................ 359
Associated Registers ................................................ 359
Configuration Register
Protection.......................................................... 362
Data EEPROM Code
Protection.......................................................... 362
Memory Code Protection .......................................... 360
Programming, Device Instructions .................................... 365
PSP. See Parallel Slave Port.
PUSH ................................................................................ 394
PWM (CCP Module) ......................................................... 173
CCPR1H:CCPR1L Registers.................................... 177
CCPR1L:CCPR1H Registers.................................... 173
Duty Cycle......................................................... 173, 177
Example Frequencies/
Resolutions ............................................... 174, 178
Period................................................................ 173, 177
Registers Associated with PWM
and Timer2........................................................ 187
Setup for PWM Operation......................................... 174
TMR2 to PR2 Match ................................. 162, 173, 177
PWM (CCP Module) and Timer2
Associated Registers ................................................ 174
PWM (ECCP Module) ....................................................... 177
Effects of a Reset...................................................... 187
Enhanced PWM Auto-Shutdown .............................. 184
Full-Bridge Application
Example ............................................................ 182
Full-Bridge Mode....................................................... 181
Direction Change .............................................. 182
Half-Bridge Mode ...................................................... 180
Half-Bridge Output Mode
Applications Example ....................................... 180
Output Configurations ............................................... 177
Output Relationships
(Active-High State)............................................ 178
Output Relationships
(Active-Low State) ............................................ 179
Programmable Dead-Band Delay............................. 184
PWM Direction Change (diagram)............................ 183
PWM Direction Change at Near 100%
Duty Cycle (diagram)........................................ 183
Setup for Operation .................................................. 187
Start-up Considerations ............................................ 186
Q
Q Clock ..................................................................... 173, 177
R
RAM. See Data Memory.
RC Oscillator....................................................................... 24
RCALL .............................................................................. 395
RCON Register................................................................. 123
RCSTA Register
SPEN Bit................................................................... 229
Register File........................................................................ 59
Register File Summary ................................................. 67–77
Registers
ADCON0 (A/D Control 0).......................................... 249
ADCON1 (A/D Control 1).......................................... 250
ADCON2 (A/D Control 2).......................................... 251
BAUDCON (Baud Rate Control)............................... 232
BIE0 (Buffer Interrupt Enable 0) ............................... 322
BnCON (TX/RX Buffer n Control,
Receive Mode) ................................................. 297
BnCON (TX/RX Buffer n Control,
Transmit Mode) ................................................ 298
BnDLC (TX/RX Buffer n Data Length
Code in Receive Mode) .................................... 304
BnDLC (TX/RX Buffer n Data Length
Code in Transmit Mode) ................................... 305
BnDm (TX/RX Buffer n Data Field Byte m
in Receive Mode).............................................. 303
BnDm (TX/RX Buffer n Data Field Byte m
in Transmit Mode)............................................. 303
BnEIDH (TX/RX Buffer n Extended
Identifier, High Byte in
Receive Mode) ................................................. 301
BnEIDH (TX/RX Buffer n Extended
Identifier, High Byte in
Transmit Mode) ................................................ 301
BnEIDL (TX/RX Buffer n Extended
Identifier, Low Byte in
Receive Mode) ................................................. 302
BnEIDL (TX/RX Buffer n Extended
Identifier, Low Byte in
Transmit Mode) ................................................ 302
BnSIDH (TX/RX Buffer n Standard
Identifier, High Byte in
Receive Mode) ................................................. 299
BnSIDH (TX/RX Buffer n Standard
Identifier, High Byte in
Transmit Mode) ................................................ 299
BnSIDL (TX/RX Buffer n Standard
Identifier, Low Byte in
Receive Mode) ................................................. 300
 2004 Microchip Technology Inc.
DS30491C-page 481