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PIC18F6585 Datasheet, PDF (50/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module | |||
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PIC18F6585/8585/6680/8680
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
RXF10SIDL(7)
RXF10SIDH(7)
RXF9EIDL(7)
RXF9EIDH(7)
RXF9SIDL(7)
RXF9SIDH(7)
RXF8EIDL(7)
RXF8EIDH(7)
RXF8SIDL(7)
RXF8SIDH(7)
RXF7EIDL(7)
RXF7EIDH(7)
RXF7SIDL(7)
RXF7SIDH(7)
RXF6EIDL(7)
RXF6EIDH(7)
RXF6SIDL(7)
RXF6SIDH(7)
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F6X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
PIC18F8X8X
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx- x-xx
xxxx xxxx
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuu- u-uu
uuuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read â0â.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read â0â.
7: This register reads all â0âs until ECAN is set up in Mode 1 or Mode 2.
DS30491C-page 48
 2004 Microchip Technology Inc.
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