PIC18F6585 Datasheet, PDF (171/496 Pages) Microchip Technology – 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with ECAN Module

PIC18F6585/8585/6680/8680
15.1 CCP Module
Both CCP1 and CCP2 are comprised of two 8-bit
registers: CCPRxL (low byte) and CCPRxH (high byte),
1 ≤ x ≤ 2. The CCPxCON register controls the
operation of CCPx. All are readable and writable.
Table 15-1 shows the timer resources of the CCP
module modes.
TABLE 15-1: CCP MODE – TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
15.2 Capture Mode
In Capture mode, CCPRxH:CCPRxL captures the
16-bit value of the TMR1 or TMR3 register when an
event occurs on pin CCPn. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCPxM3:CCPxM0
(CCPxCON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCPxIF (PIR registers), is set. It
must be cleared in software. If another capture occurs
before the value in register CCPRx is read, the old
captured value will be lost.
15.2.1 CCP PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the appropriate TRIS bit.
Note:
If the CCPx is configured as an output, a
write to the port can cause a capture
condition.
15.2.2 TIMER1/TIMER3 MODE SELECTION
The timer used with each CCP module is selected in
the T3CCP2:T3CCP1 bits of the T3CON register. The
timers used with the capture feature (either Timer1 or
Timer3) must be running in Timer mode or Synchro-
nized Counter mode. In Asynchronous Counter mode,
the capture operation may not work.
TABLE 15-2: INTERACTION OF CCP MODULES
CCP1
Mode
CCP2
Mode
Interaction
Capture
Capture
Compare
PWM
PWM
PWM
Capture
Compare
Compare
PWM
Capture
Compare
TMR1 or TMR3 time base. Time base can be different for each CCP.
The compare could be configured for the special event trigger which clears either TMR1
or TMR3 depending upon which time base is used.
The compare(s) could be configured for the special event trigger which clears TMR1 or
TMR3 depending upon which time base is used.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
None.
None.
 2004 Microchip Technology Inc.
DS30491C-page 169